1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display employing an on-common type storage capacitor for providing a uniform orientation film and improving the optical characteristic thereof by reducing the step height of a pixel electrode, and a method of fabricating the same.
2. Discussion of the Background Art
For a long time, a cathode ray tube (CRT) display has been used as a display for displaying image information on a screen, but its large volume and heavy weight compared with the display area create inconveniences and difficulties in using it.
For this reason, a thin flat type display that can be used anywhere because of its large display area and reduced thickness was developed and is now replacing the CRT. In particular, a liquid crystal display (LCD) is the one that has a characteristic of having higher resolution than other types of flat displays, and a rapid response speed comparable to the display quality of the CRT when displaying moving images.
As widely known, the driving principle of the LCD is based on the optical anisotropy and polarization. If an electromagnetic field is applied from the outside to the liquid crystal molecules that are thin and long in their structure and have orientation and polarization in their alignment, the alignment direction of the liquid crystal molecules can be artificially adjusted. Therefore, the artificial control of their alignment direction allows light to be transmitted or blocked depending on the alignment direction of the liquid crystal molecules and thereby, colors and images can be displayed.
An active matrix liquid crystal display in which a non-linear characteristic active device is formed at each of pixels arranged in a matrix configuration controls the operation of each pixel by using the switching characteristic of the active device, and realizes a memory function by an electro-optical effect of the liquid crystal.
In the active matrix liquid crystal display, it is required to maintain a signal voltage input through the signal lines at a constant level for a predetermined time until the next input of another signal so as to secure the uniformity of the displayed images. For this requirement, a storage capacitor should be formed in parallel with the liquid crystal cells.
Here, the storage capacitor formed on the liquid crystal display can be divided into on-common type and on-gate type depending on the type of electrode used.
In view of the difference between these two types of storage capacitors, the on-gate type has advantages of little decrease of the aperture ratio because it uses a part of the (n−1)-th scanning line as a charge electrode of the n-th pixel, unnoticeable characteristic in case of the occurrence of point defects in normally white (NW) mode, and good production yield, but has disadvantages of a long scanning signal time.
Meanwhile, the on-common type, which uses a charge electrode separately, has an advantage of a short scanning signal time, but has disadvantages of substantial decrease of the aperture ratio, and noticeable characteristic in case of the occurrence of point defects in NW mode, which results in low production yield.
The on-common type storage capacitor is briefly described with reference to FIG. 1. FIG. 1 is a schematic diagram of a thin film transistor (TFT) array including on-common type storage capacitors provided in a conventional liquid crystal display.
Referring to FIG. 1, a TFT array with an on-common type storage capacitor has an intersection part defined by the crossing of scanning lines 109, 119 and signal lines 110, 120, on an insulating substrate (a lower substrate). At the portion crossed by a signal line (ex. 110) and a scanning line (ex. 119), there is formed a thin film transistor (TFT) including a source electrode 111 (extended from signal line 110) and a drain electrode 112, a gate electrode 114 (extended from scanning line 119) and a semiconductor layer 113.
In addition, a pixel electrode 115 is connected to the drain electrode 112 and spaced apart by a constant interval from the scanning line 119 and the signal line 110. A lower storage electrode 116 is placed to cross the pixel electrode 115 in parallel with the scanning line 119.
The on-common type storage capacitor structured as described above accumulates charges between the pixel electrode 115 functioning as the upper storage electrode and the lower storage electrode 116 formed of the same material as the gate electrode 114.
The electrostatic capacitance accumulated in the storage capacitor can be represented as follows.
  C  =      ε    ⁢          A      d      
The electrostatic capacitance is calculated by the above equation. Here, C is an electrostatic capacitance, ε is a dielectric constant, A is the area of the electrode, and d is the interval between the electrodes.
To secure the uniformity of the images displayed on the liquid crystal display, the greater the capacitance of the storage capacitor the better the result.
As one means of achieving this, an additional upper storage electrode is formed below the pixel electrode as shown in FIGS. 2 and 3, to reduce the interval (d) between the electrodes and to increase the capacitance.
FIG. 2 is a schematic diagram of the TFT array of an improved on-common type storage capacitor used in a liquid crystal display of the background art, and FIG. 3 is a detailed sectional view of the portion “A” in FIG. 2.
As shown in FIGS. 2 and 3, the TFT array of an improved on-common type storage capacitor is similar in structure to that shown in FIG. 1. Therefore, the same reference numerals are used to refer to the same or like parts, and an additional description will be made here for different parts.
The basic structure of the TFT array of an improved on-common type storage capacitor is similar to the structure of the TFT array shown in FIG. 1, but only the upper storage electrode 217 is changed.
As shown in FIGS. 2 and 3, the upper storage electrode 217 (having a predetermined size) is formed in the same layer that the signal line 110 is formed by using the same material as the signal line 110.
In addition, a through hole region 305 for a through hole is provided in a part of a passivation film 303 covering the upper storage electrode 217. The pixel electrode 115 and the upper storage electrode 217 are electrically connected through the through hole region 305.
The improved on-common type storage capacitor structured as above has charges accumulated between the upper storage electrode 217 (having the same material as the signal line 110), and the lower storage electrode 116, having the same material as the gate electrode 114.
In comparison with the on-common type storage capacitor shown in FIG. 1, the interval between the two electrodes forming the storage capacitor is reduced and thus, a relatively large capacitance can be secured.
Now hereinafter, a method of fabricating a TFT array of the improved on-common storage capacitor is briefly illustrated with reference to FIGS. 2 to 4.
FIG. 4 is a flow diagram depicting a method of fabricating the TFT array of the improved on-common type of storage capacitor used in a liquid crystal display of the Background Art. Here, general processing steps of fabricating a TFT array are omitted, and the method described herein focuses primarily on the region of the on-common type storage capacitor.
First, there is provided on a substrate, a plurality of scanning lines 109, 119 and an on-common type lower storage electrode 116 (of a predetermined size) in parallel with the plurality of scanning lines 109, 119 (step 401). Here, the plurality of scanning lines 109, 119 and the on-common type lower storage electrode 116 in parallel with the plurality of the scanning lines 109, 119 are formed of the same material as the gate electrode 114 during the formation of the gate electrode 114, and thus, a separate masking process is not necessary. An insulating layer 301 is formed on the plurality of scanning lines 109, 119, the lower storage electrode 116, and the gate electrode 114 (step 402).
Then, an on-common type upper storage electrode 217 is formed on the on-common type storage lower substrate 116, and a plurality of signal lines 110, 120 are formed to cross the plurality of scanning lines 109 and the 119 at a right angle (step 403). The upper storage electrode 217 and the plurality of signal lines 110, 120 are formed of the same material as the source/drain electrode 111, 112 during the formation of the source/drain electrode 111, 112, and thus, a separate masking process is not necessary. Then, a passivation film 303 is formed on the plurality of signal lines 110, 120, the upper storage electrode 217, and the source/drain electrode 111, 112 (step 404).
At a predetermined region of the passivation film 303 formed on the upper storage electrode 217, a through-hole is formed (step 405), and then, a pixel electrode is formed at the matrix-shaped region defined by the plurality of scanning lines 109, 119 and the plurality of signal lines 110, 120 (step 406).
The pixel electrode 115 formed on the passivation film 303, and the upper storage electrode 217 can be electrically connected via the through-hole region 305. Accordingly, the electrostatic capacitance of the on-common type storage capacitor can be increased more than the electrostatic capacitance of the on-common type storage capacitor in FIG. 1, by accumulating charges between the lower storage electrode 116 and the upper storage electrode 217.
However, the TFT array of the improved on-common type storage capacitor structured as shown in FIG. 3 has a large step height in the pixel electrode 115 (especially, in the through hole region). Therefore, when forming an orientation film for alignment of liquid crystal, a problem occurs in that the orientation film may not be formed uniformly. In case the orientation film is not uniform, the liquid crystal molecules are not aligned properly, and an optical failure such as light leakage may occur.
To form the TFT array as shown in FIG. 3, the through hole is formed as illustrated in the steps 405 and 406, and the pixel electrode 115 and the upper storage electrode 217 are connected electrically via the through-hole region 305. In the step 405, an etch process is performed to form the through-hole in the predetermined region of the passivation film 303.
However, a point defect may be generated by a nonuniform etch when forming the through hole by the etch process and exposing the upper storage electrode 217. Therefore, resistance may be increased when electrically connecting the upper electrode 217 and the pixel electrode 115, and finally, a white defect may be generated in the pixel to display images, and the TFT array ends up with a failure.